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journal article·2024-06

Optimization of Dual Material Based Dielectric Modulated Heterojunction Double Gate Tunnel FETs with Noise Reduction Analysis for High Frequency Applications

Vedvrat, Mohd Yusuf Yasin, Digvijay Pandey

Silicon· Volume 16· Issue 9
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OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Silicon Carbide Semiconductor Technologies

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References (47)

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1. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high k gate dielectric. IEEE Trans Electron Devices 54:1725–1733. https://doi.org/10.1109/TED.2007.89938910.1109/TED.2007.899389 ↗
2. Sivasankaran K, Mallick PS (2013) A comparative study of radio frequency stability performance of double gate MOSFET and double gate tunnel FET. Proc 013 Int Conf Green Comput Commun Conserv Energy, ICGCE, 220–224. https://doi.org/10.1109/ICGCE.2013.682343210.1109/ICGCE.2013.6823432 ↗
3. Pal A, Dutta AK (2016) Analytical drain current modeling of double gate tunnel field-effect transistors. IEEE Trans Electron Devices 63:3213–3221. https://doi.org/10.1109/TED.2016.258184210.1109/TED.2016.2581842 ↗
4. Vedvrat, Yasin MY, Gupta V, Pandey D (2023) Improved switching and analog/RF behaviour of SiGe heterojunction dielectric modulated dual material nano silicon tunnel FET for low power applications. SILICON 16:1297–1308. https://doi.org/10.1007/s12633-023-02755-210.1007/s12633-023-02755-2 ↗
5. Yang Zhaonian (2016) Tunnel field-effect transistor with an L shaped gate. IEEE Electron Device Lett 37:839–842. https://doi.org/10.1109/LED.2016.257482110.1109/LED.2016.2574821 ↗
6. Bhuwalka KK, Sedlmaier S (2004) Vertical tunnel field-effect transistor. IEEE Trans Electron Devices 51:279–282. https://doi.org/10.1109/TED.2003.82157510.1109/TED.2003.821575 ↗
7. Paras N, Chauhan SS (2019) Temperature sensitivity analysis of vertical tunneling based dual metal Gate TFET on analog/RF FOMs. Appl Phys A 125(5):31610.1007/s00339-019-2621-x ↗
8. Liana Z, Choudhuri B, Bhowmick B (2023) Analysis of the impact of interface trap charges on the analog/RF performance of a graphene nanoribbon vertical tunnel FET. J Electron Mater 52(10):6825–6839. https://doi.org/10.1007/s11664-023-10615-310.1007/s11664-023-10615-3 ↗
9. Bhushan B, Nayak K, Rao VR (2012) DC compact model for SOI tunnel field-effect transistors. IEEE Trans Electron Devices 59:2635–2642. https://doi.org/10.1109/TED.2012.220918010.1109/TED.2012.2209180 ↗
10. Kao KH, William ASV, Vandenberghe G et al (2012) Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans Electron Devices 59:292–30110.1109/TED.2011.2175228 ↗
11. Kim HW, Kim JH, Kim SW, Sun MC, Park E, Park BG (2014) Tunneling field-effect transistor with Si/SiGe material for high current drivability. Jpn J Appl Phys 53:6S. https://doi.org/10.7567/JJAP.53.06JE1210.7567/JJAP.53.06JE12 ↗
12. Mitra SK, Goswami R, Bhowmick B (2016) A hetero dielectric stack gate SOI-TFET with back gate and its application as a digital inverter. Superlattices Microstruct 92:37–51. https://doi.org/10.1016/j.spmi.2016.01.04010.1016/j.spmi.2016.01.040 ↗
13. Ahish S, Sharma D, Vasantha MH, Kumar YBN (2016) Design and analysis of novel InSb/Si heterojunction Double Gate tunnel field effect transistor. IEEE Comput Soc Annu Symp VLSI.105–109. https://doi.org/10.1109/ISVLSI.2016.5210.1109/ISVLSI.2016.52 ↗
14. Priya GL, Balamurugan N (2019) New dual material double gate junctionless tunnel FET: subthreshold modeling and simulation. AEU- Int J Electron Commun 99:130–138. https://doi.org/10.1016/j.aeue.2018.11.03710.1016/j.aeue.2018.11.037 ↗
15. Saurabh S, Kumar M (2011) Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans Electron Devices 58:404–410. https://doi.org/10.1109/TED.2010.209314210.1109/TED.2010.2093142 ↗
16. Pravin J, Nirmal D, Prajoon P, Ajayan J (2016) Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications. Phys E Low-Dimens Syst Nanostruct 83:95–100. https://doi.org/10.1016/j.physe.2016.04.01710.1016/j.physe.2016.04.017 ↗
17. Sharma N, Chauhan SS (2017) Dual metal drain Ge-source dopingless TFET with enhanced turn-ON steep subthreshold swing and high ON-current. Electron Lett 53(14):960–96210.1049/el.2017.0157 ↗
18. Kumar S, Yadav DS (2022) Assessment of interface trap charges on proposed tfet for low power high-frequency application. SILICON 14(15):9291–9304. https://doi.org/10.1007/s12633-021-01616-010.1007/s12633-021-01616-0 ↗
19. Verhulst AS, Sorée B, Leonelli D (2010) Modeling the single gate, double-gate, and gate-all-around tunnel field-effect transistor. J Appl Phys 107:24518. https://doi.org/10.1063/1.327704410.1063/1.3277044 ↗
20. Gupta SK, Kumar S (2019) Analytical modeling of a triple material double gate TFET with hetero-dielectric gate stack. SILICON 11(3):1355–1369. https://doi.org/10.1007/s12633-018-9932-y10.1007/s12633-018-9932-y ↗
21. Dutta U, Soni M, Pattanaik M (2019) Simulation study of hetero dielectric tri material gate tunnel FET based common source amplifier circuit. AEU- Int J Electron Commun 99:258–263. https://doi.org/10.1016/j.aeue.2018.12.00410.1016/j.aeue.2018.12.004 ↗
22. Raad BR, Nigam K, Sharma D, Kondekar PN (2016) Performance investigation of the bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement. Superlattice Microstruct 94:138–146. https://doi.org/10.1016/j.spmi.2016.04.01610.1016/j.spmi.2016.04.016 ↗
23. Kumar S, Goel E, Singh K, Singh B, Kumar M, Jit S (2016) A compact 2-D analytical model for electrical characteristics of double-gate tunnel field-effect transistors with a SiO2/high-stacked gate-oxide structure. IEEE Trans Electron Devices 63(8):3291–3299. https://doi.org/10.1109/TED.2016.257261010.1109/TED.2016.2572610 ↗
24. Goel E, Kumar S, Singh K, Singh B, Kumar M, Jit S (2016) 2-D analytical modeling of threshold voltage for graded-channel dual material double-gate MOSFETs. IEEE Trans Electron Devices 63(3):966–973. https://doi.org/10.1109/TED.2016.252009610.1109/TED.2016.2520096 ↗
25. Anand S, Sarin RK (2017) Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance. J Semicond 38(2):02400110.1088/1674-4926/38/2/024001 ↗
26. Choi WY, Lee HK (2016) Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Nano Converg 3:1310.1186/s40580-016-0073-y ↗
27. Gracia D, Nirmal D, Nisha Justeena A (2017) Investigation of Ge based double gate dual metal tunnel FET novel architecture using various hetero dielectric materials. Superlattice Microstruct S0749–6036(17):30824–30828
28. Sahu SA, Goswami R, Mohapatra SK (2019) Characteristic enhancement of hetero dielectric DG TFET using SiGe pocket at source/channel interface: proposal and investigation. Silicon 12(3):513–520. https://doi.org/10.1007/s12633-019-00159-910.1007/s12633-019-00159-9 ↗
29. Rani C, Bagan KB, Nirmal D, Roach RS (2019) Enhancement of performance in TFET by reducing high-K dielectric length and drain electrode thickness. Silicon 12(10):2337–2343. https://doi.org/10.1007/s12633-019-00328-w10.1007/s12633-019-00328-w ↗
30. Karbalaei M, Dideban D, Heidari H (2020) A simulation study of the influence of a high-k insulator and source stack on the performance of a double-gate tunnel FET. J Comput Electron 19(3):1077–108410.1007/s10825-020-01497-3 ↗
31. Nigam K, Kondekar PN, Sharma D (2016) Approach for ambipolar behavior suppression in tunnel FET by work function engineering. Micro Nano Lett 11(8):460–46410.1049/mnl.2016.0178 ↗
32. Kondekar PN, Nigam K, Pandey S, Sharma D (2017) Design and analysis of polarity controlled electrically doped tunnel FET with bandgap engineering for analog/RF applications. IEEE Trans Electron Devices 64(2):412–41810.1109/TED.2016.2637638 ↗
33. Chandan BV, Dasari S, Yadav S (2018) Approach to suppress ambipolarity and improve RF and linearity performances on ED tunnel FET. Micro Nano Lett 13(5):684–68910.1049/mnl.2017.0814 ↗
34. Lv Y, Huang Q, Wang H, Chang S, He J (2016) A numerical study on grapheme nano ribbon heterojunction dual-material gate tunnel FET. IEEE Electron Device Lett 37:1354–135710.1109/LED.2016.2597155 ↗
35. Gopal G, Agrawal H, Garg H, Varma T (2023) Simulation-based analysis of an L-patterned negative-capacitance dual tunnel VTFET. Int J Electron 1–18. https://doi.org/10.1080/00207217.2022.216406910.1080/00207217.2022.2164069 ↗
36. Gopal G, Varma T (2023) Impact of temperature on the reliability of UTB-DG-FE-TFETs and their RF/analog and linearity parameter dependence. J Electron Mater 52(9):6293–6307. https://doi.org/10.1007/s11664-023-10556-x10.1007/s11664-023-10556-x ↗
37. Gopal G, Garg H, Agrawal H, Varma T (2022) Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance. Semicond Sci Technol 37(10):105006. https://doi.org/10.1088/1361-6641/ac830b10.1088/1361-6641/ac830b ↗
38. Gopal G, Varma T (2022) Simulation-based analysis of ultra thin-body double gate ferroelectric TFET for an enhanced electric performance. SILICON 14(12):6553–6563. https://doi.org/10.1007/s12633-021-01428-210.1007/s12633-021-01428-2 ↗
39. Neves FS, Agopianand PGD, Martino JA, Cretu B, Rooyackers R, Vandooren A, Simoen E, Thean AV, Claeys C (2016) Low frequency noise analysis and modeling in vertical Tunnel FETs with Ge source. IEEE Trans Electron Devices 63:1658–1665. https://doi.org/10.1109/TED.2016.253336010.1109/TED.2016.2533360 ↗
40. Pandey R, Rajamohanan B, Liu H, Narayanan V, Datta S (2014) Electrical noise in heterojunction interband tunnel FETs. IEEE Trans Electron Devices 61:552–56010.1109/TED.2013.2293497 ↗
41. ATLAS Device Simulation Software (2013) Silvaco Int., Santa. Clara, CA, Version 5.14.0.R
42. Shockley W, Read WT (1952) Statistics of the recombination of holes and electrons. Phys Rev 87:835–84210.1103/PhysRev.87.835 ↗
43. Lee G, Jang JS, Choi WY (2013) Dual-dielectric-constant spacer hetero-gate-dielectric tunneling field-effect transistors. Semicond Sci Technol 28(5):052001. https://doi.org/10.1088/0268-1242/28/5/05200110.1088/0268-1242/28/5/052001 ↗
44. Cui N, Liang R, Wang J, Xu J (2012) Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering. AIP Adv 2(2). https://doi.org/10.1063/1.470539810.1063/1.4705398 ↗
45. Na KY, Kim YS (2006) Silicon complementary metal–oxide–semiconductor field-effect transistors with dual work function gate. Jpn J Appl Phys 45(12R):9033. https://doi.org/10.1143/JJAP.45.903310.1143/JJAP.45.9033 ↗
46. Padilla JL, Gamiz F, Godoy A (2012) A simple approach to quantum confinement in tunneling field-effect transistors. IEEE Electron Device Lett 33(10):1342–1344. https://doi.org/10.1109/LED.2012.220787610.1109/LED.2012.2207876 ↗
47. Padilla JL, Gamiz F, Godoy A (2012) Impact of quantum confinement on gate threshold voltage and subthreshold swings in double-gate tunnel FETs. IEEE Trans Electron Devices 59(12):3205–3211. https://doi.org/10.1109/TED.2012.221653110.1109/TED.2012.2216531 ↗