journal article·2022-12

Improved Switching Current Ratio with Workfuncion Modulated Junctionless FinFET

Mitali Rathi, Guru Prasad Mishra

Silicon· Volume 14· Issue 18
Publisher page

Abstract

This work presents a new junctionless device called Workfunction Modulated Dual Metal Gate Junctionless FinFET (WFMDMG-Junctionless FinFET) to minimize the short channel effects, and to achieve improved dc performance. The result is analyzed by dividing the workfunction of the gate metal electrode in two equal halves and further dividing the source end of the electrode in five equal parts with linear variation in workfunction, keeping the drain end at constant workfunction. The 3-D TCAD simulations are carried out by SILVACO TCAD tool. And the results are compared with the Single Metal Gate (SMG)-junctionless FinFET, and Dual Metal Gate (DMG)-junctionless FinFET. The new proposed junctionless device shows improved subthreshold characteristics, i.e., minimum subthreshold swing (SS) of 60.1 mV/decade, and high ION/IOFF current ratio of 1.48e13.
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Research context

OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Integrated Circuits and Semiconductor Failure Analysis

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References (37)

Show source-provided references
1. Nayak D, Acharya DP, Mahapatra K (2017) A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor. AEU-Int J Electron Commun 74:192–197. https://doi.org/10.1016/j.aeue.2017.02.01210.1016/j.aeue.2017.02.012 ↗
2. Gupta A, Mathur R, Nizamuddin M (2019) Design, simulation, and comparative analysis of a novel FinFET based astable multivibrator. AEU-Internat J Electron Commun 100:163–171. https://doi.org/10.1016/j.aeue.2018.12.00710.1016/j.aeue.2018.12.007 ↗
3. Suzuki K, Tanaka T, Tosaka Y, Horie H, Arimoto Y (1993) Scaling theory for double-gate SOI MOSFET’s. IEEE Trans Electron Devices 40(12):2326–2329. https://doi.org/10.1109/16.24948210.1109/16.249482 ↗
4. Suzuki E, Ishii K, Kanemaru S, Maeda T, Tsutsumi T, Sekigawa T, Kiyoko N, Hiroshima H Highly suppressed short-channel effects in ultrathin SOI n-MOSFET’s. IEEE Transactions Electron Devices 47(2):354–359. https://doi.org/10.1109/16.82228010.1109/16.822280 ↗
5. Breed A, Roenker KP (2005) Comparison of the scaling characteristics of nanoscale silicon N-channel multiple-gate MOSFETs. In 48th Midwest Symposium on Circuits and Systems, 603–6 IEEE. https://doi.org/10.1109/MWSCAS.2005.159417310.1109/MWSCAS.2005.1594173 ↗
6. Ferain I, Colinge CA, Colinge JP (2011) Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. Nature. 479:310–316. https://doi.org/10.1038/nature1067610.1038/nature10676 ↗
7. Colinge JP (2004) Multiple-gate SOI MOSFETs. Solid State Electron 48:897–905. https://doi.org/10.1016/j.sse.2003.12.02010.1016/j.sse.2003.12.020 ↗
8. Razavieh A, Zeitzoff P, Nowak EJ (2019) Challenges and limitations of CMOS scaling for FinFET and beyond architectures. IEEE Trans Nanotechnol 18:999–1004. https://doi.org/10.1109/TNANO.2019.294245610.1109/TNANO.2019.2942456 ↗
9. Bhattacharya D, Jha NK (2015) FinFETs: From devices to architectures. Digit Analog Analog Digit IC Des:21–55. https://doi.org/10.1155/2014/36568910.1155/2014/365689 ↗
10. Hisamoto D, Lee W, Kedzierski J, Takeuchi H, Asano K, Kuo C, Anderson E, King TJ, Bokor J, Hu C (2010) FinFET — a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans Electron Devices 47:2320–2325. https://doi.org/10.1109/16.88701410.1109/16.887014 ↗
11. Sun X, Moroz V, Damrongplasit N, Shin C, Liu TJK (2011) Variation study of the planar ground-plane bulk MOSFET, SOI FinFET, and trigate bulk MOSFET designs. IEEE Trans Electron Devices 58(10):3294–3299. https://doi.org/10.1109/TED.2011.216147910.1109/TED.2011.2161479 ↗
12. Pal RS, Sharma S, Dasgupta S (2017) Recent trend of FinFET devices and its challenges: a review. Conf Emerg Devices Smart Syst ICEDSS 2017:150–154. https://doi.org/10.1109/ICEDSS.2017.807367510.1109/ICEDSS.2017.8073675 ↗
13. Sinha S, Yeric G, Chandra V, Cline B, Cao Y (2012) Exploring sub-20nm FinFET design with predictive technology models. Proc - Des Autom Conf 283–288. https://doi.org/10.1145/2228360.222841410.1145/2228360.2228414 ↗
14. Chiang MH, Lin JN, Kim K, Te CC (2008) Optimal design of triple-gate devices for high-performance and low-power applications. IEEE Trans Electron Devices. 55:2423–2428. https://doi.org/10.1109/TED.2008.92766410.1109/TED.2008.927664 ↗
15. Rajendran S, Lourde RM (2015) FinFETs and their Application as Load Switches in Micromechatronics. Proc - 2015. IEEE Int Symp Nanoelectron Inf Syst iNIS 152–157. https://doi.org/10.1109/iNIS.2015.5110.1109/iNIS.2015.51 ↗
16. Nagateja T, Srinivasulu A, Di P (2019) RF harvesting system for low-power applications using FinFETs. IEEE Int Conf Consum Electron ICCE 1–6. https://doi.org/10.1109/ICCE.2019.866183810.1109/ICCE.2019.8661838 ↗
17. Banerjee K, Biswas A (2020) Improved digital performance of charge plasma based junctionless C-FinFETs at 10 nm technology node and beyond. AEU-Intern J Electron Commun 124:153350. https://doi.org/10.1016/j.aeue.2020.15335010.1016/j.aeue.2020.153350 ↗
18. Lee J, Kim Y, Cho S (2016) Design of poly-Si junctionless fin-channel FET with quantum-mechanical drift-diffusion models for sub-10-nm technology nodes. IEEE Trans Electron Devices 63(12):4610–4616. https://doi.org/10.1109/TED.2016.261499010.1109/TED.2016.2614990 ↗
19. Han MH, Chang CY, Chen HB, Wu JJ, Cheng YC, Wu YC (2013) Performance comparison between bulk and SOI junctionless transistors. IEEE Electron Device Lett 34(2):169–171. https://doi.org/10.1109/LED.2012.223139510.1109/LED.2012.2231395 ↗
20. Jegadheesan V, Sivasankaran K, Konar A (2020) Improved statistical variability and delay performance with junctionless inserted oxide FinFET. AEU-Intern J Electron Commun 115:153030. https://doi.org/10.1016/j.aeue.2019.15303010.1016/j.aeue.2019.153030 ↗
21. Thirunavukkarasu V, Jhan YR, Liu YB, Wu YC (2015) Performance of inversion, accumulation, and junctionless mode n-type and p-type bulk silicon FinFETs with 3-nm gate length. IEEE Electron Device Letters 36(7):645–647. https://doi.org/10.1109/LED.2015.243330310.1109/LED.2015.2433303 ↗
22. Nawaz SM, Dutta S, Mallik A (2015) Comparison of gate-metal Workfunction variability between Ge and Si p-channel FinFETs. IEEE Trans Electron Devices 62:3951–3956. https://doi.org/10.1109/TED.2015.248810110.1109/TED.2015.2488101 ↗
23. Endo K, Uchi O, SI, Ishikawa Y, Liu Y, Matsukawa T, Sakamoto K, Tsukada J, Yamauchi H, Masahara M. (2010) Variability analysis of TiN metal-gate FinFETs. IEEE Electron Device Lett 31:546–548. https://doi.org/10.1063/1.480304010.1063/1.4803040 ↗
24. Liu Y, Kijima S, Sugimata E, Masahara M, Endo K, Matsukawa T, Ishii K, Sakamoto K, Sekigawa T, Yamauchi H, Takanashi Y (2006) Investigation of the TiN gate electrode with tunable workfunction and its application for FinFET fabrication. IEEE Trans Nanotechnol 5:723–730. https://doi.org/10.1109/TNANO.2006.88503510.1109/TNANO.2006.885035 ↗
25. Matsukawa T, Endo K, Liu Y, O’uchi S, Ishikawa Y, Yamauchi H, Tsukada J, Ishii K, Masahara M, Sakamoto K, Suzuki E. (2008) Threshold-voltage reduction of FinFETs by ta/Mo interdiffusion dual metal-gate technology for low-operating-power application. IEEE Trans Electron Devices 55:2454–2461. https://doi.org/10.1109/TED.2008.92764810.1109/TED.2008.927648 ↗
26. Matsukawa T, Endo K, Liu Y, O’uchi S, Ishikawa Y, Yamauchi H, Tsukada J, Ishii K, Masahara M, Sakamoto K, Suzuki E (2008) A Ta/Mo interdiffusion dual metal gate technology for drivability enhancement of FinFETs. IEEE Electron Device Lett 29:618–620. https://doi.org/10.1109/LED.2008.92296510.1109/LED.2008.922965 ↗
27. King T, Pfiester JR, Member S, Saraswat KC (1991). A Variable-Work-Funct Polycrystalline- CMOS Technol 12:533–535. https://doi.org/10.1109/55.11918010.1109/55.119180 ↗
28. Li TL, Hu CH, Ho WL, Wang HCH, Chang CY (2005) Continuous and precise workfunction adjustment for integratable dual metal gate CMOS technology using Hf-Mo binary alloys. IEEE Trans Electron Devices. 52(6):1172–1179. https://doi.org/10.1109/TED.2005.84810810.1109/TED.2005.848108 ↗
29. Pan A, Liu R, Sun M, Ning CZ (2010) Spatial composition grading of quaternary ZnCdSSe alloy nanowires with tunable light emission between 350 and 710 nm on a single substrate. ACS Nano 4:671–680. https://doi.org/10.1021/nn901699h10.1021/nn901699h ↗
30. Jena B, Dash S, Mishra GP (2016) Electrostatic performance improvement of dual material cylindrical gate MOSFET using work-function modulation technique. Superlattice Microst 97:212–220. https://doi.org/10.1016/j.spmi.2016.06.02410.1016/j.spmi.2016.06.024 ↗
31. Daga M, Mishra GP (2021) Improvement in electrostatic effeciency using workfunction modulated dual metal gate FinFET. Mater Today: Proc 43:33443–33446. https://doi.org/10.1016/j.matpr.2020.09.08210.1016/j.matpr.2020.09.082 ↗
32. Daga M, Mishra GP (2021) Subthreshold performance improvement of underlapped FinFET using Workfunction modulated dual-metal gate technique. Silicon. 13(5):1541–1548. https://doi.org/10.1007/s12633-020-00550-x10.1007/s12633-020-00550-x ↗
33. Mishra S, Bhanja U, Mishra GP (2019) Variation of source gate workfunction on the performance of dual material gate rectangular recessed channel SOI-MOSFET. Int J Numer Model Electron Netw Devices Fields 32(1):e2487. https://doi.org/10.1002/jnm.248710.1002/jnm.2487 ↗
34. Santa Clara, CA (2015) ATLAS User’s manual device simulation software: Silvaco Int. USA
35. Yeo YC, King TJ, Hu C (2003) MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations. IEEE Trans Electron Devices 50:1027–1035. https://doi.org. https://doi.org/10.1109/TED.2003.81250410.1109/TED.2003.812504 ↗
36. Samal A, Pradhan KP, Mohapatra S (2021) Improvising the switching ratio through low-k/high-k spacer and dielectric gate stack in 3D FinFET-a simulation perspective. Silicon. 13(8):2655–2660. https://doi.org/10.1007/s12633-020-00618-810.1007/s12633-020-00618-8 ↗
37. Vandana B, Das JK, Mohapatra SK, Kaushik BK (2017) Effectiveness of high permittivity spacer for underlap regions of wavy-Junctionless FinFET at 22 nm node and scaling Short Channel effects. In international symposium on VLSI design and test, vol 2017. Springer, Berlin, pp 545–556