Surface Potential Modeling and Performance Investigation of Delta Doped DMG SOI MOSFET for Improved AF Parameters
Source abstract
Abstract
A two–dimensional (2D) analytical model with surface potential variation in the delta doped dual material gate with fully depleted silicon on insulator-MOSFET (DMG-FD-SOI MOSFET) designed to evaluate the RF/AF performance. A novel delta doped is introduced in proposed device to enhance the analog performance, and the effect of transconductance and voltage gain is explored to investigate several structure characteristics. The impact of silicon thickness, source concentration, and work-function deviation is examined to study the numerous structure performance metrics simulation in silvaco. Furthermore, threshold voltage (({V}th)), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS) and capacitance variations are examined. The result revealed that the proposed device reduces the SCEs, raised transconductance ((gm)), and improved ({I}on) with increased (gm/gd) compared to SMG-SOI MOSFET. The increased silicon thickness and channel doping (1 × 1017/cm3) enhanced the device threshold voltage from standardized 0.25 V value (over thickness = 10 nm) and ({I}on) to ({I}off) ratio, whereas the capacitances (({C}gs) and ({C}gd)) and DIBL were found reduced. This work explained the advantages of delta doped DMG-FD-SOI MOSFET device over a single material gate structure as well as gives a motivation for additional exploratory investigation.
Source: expertdata · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices · Integrated Circuits and Semiconductor Failure Analysis
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (21)
Show source-provided references
1. Morris DH, Avci UE, Young IA, Intel Corp (2019) Tunnel field-effect transistor (tfet) based high-density and low-power sequential. U.S. Patent Application 15/992, 080
2. Wadhwa G, Raj B (2018) Parametric variation analysis of symmetric double gate charge plasma JLTFET for biosensor application. IEEE Sens J 18(15):6070–607710.1109/JSEN.2018.2846409 ↗
3. Wadhwa G, Singh J, Raj B (2021) Design and investigation of doped triple metal double gate vertical TFET for performance enhancement. SILICON 13(6):1839–184910.1007/s12633-020-00585-0 ↗
4. Wadhwa G, Raj B (2019) Design, simulation and performance analysis of JLTFET biosensor for high sensitivity. IEEE Trans Nanotechnol 18:567–574. https://doi.org/10.1109/TNANO.2019.291819210.1109/TNANO.2019.2918192 ↗
5. Voldman S, Hui D, Warriner L, Young D, Williams R, Howard J, Gross V, Rausch W, Leobangdung E, Sherony M, Rohrer N (1999) Electrostatic discharge protection in silicon-on-insulator technology. In 1999 IEEE International SOI Conference. Proceedings (Cat. No. 99CH36345), pp. 68–71, October. IEEE10.1109/SOI.1999.819858 ↗
6. Long W, Haijiang O, Kuo J-M, Chin KK (1999) Dual-material gate (DMG) field effect transistor. IEEE Trans Electron Devices 46:865–87010.1109/16.760391 ↗
7. Wadhwa G, Raj B (2018) Label free detection of biomolecules using charge-plasma-based gate underlap dielectric modulated junctionless TFET. J Electron Mater 47(8):4683–469310.1007/s11664-018-6343-1 ↗
8. Chaudhry A, Kumar MJ (2004) Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Trans Device Mater Reliab 4(1):99–10910.1109/TDMR.2004.824359 ↗
9. Rewari S, Nath V, Haldar S, Deswal SS, Gupta RS (2017) Gate-induced drain leakage reduction in cylindrical dual-metal hetero-dielectric gate all around MOSFET. IEEE Trans Electron Devices 65(1):3–10
10. Trivedi VP, Fossum JG (2004) Nanoscale FD/SOI CMOS: thick or thin box. IEEE Electron Device Lett 26(1):26–2810.1109/LED.2004.839624 ↗
11. Grenouillet L, Vinet M, Gimbert J (2012) UTBB FDSOI transistors with dual STI and shrinked back gate architecture for a multi-VT strategy at 20nm node and below, In: Technical Digest of International Electron Devices Meeting, San Francisco, 64–6
12. Balestra F, Cristoloveanu S, Benachir M, Brini J, Elewa T (1987) Double-gate silicon-on insulator transistor with volume inversion: a new device with greatly enhaced performance. IEEE Electron Device Lett EDL 8(9):410–41210.1109/EDL.1987.26677 ↗
13. Zhou X, Long W (1998) A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology. IEEE Trans Electron Devices 45:2546–254810.1109/16.735743 ↗
14. Faynot O, Andrieu F, Weber O, Fenouillet-Béranger C, Perreau P, Mazurier J, Benoist T, Rozeau O, Poiroux T, Vinet M, Grenouillet L (2010) Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond. In 2010 International Electron Devices Meeting, pp. 3–2, IEEE.10.1109/IEDM.2010.5703287 ↗
15. Ishigaki T, Tsuchiya R, Morita Y, Yoshimoto H, Sugii N, Iwamatsu T, Oda H, Inoue Y, Ohtou T, Hiramoto T, Kimura S (2009) Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster. Solid-State Electron 53(7):717–72210.1016/j.sse.2009.02.008 ↗
16. Kumar MJ, Chaudhry A (2004) Two-dimensional analytical modeling of fully depleted Dual-Material Gate (DMG) SOI MOSFET and evidence for diminished short-channel effects. IEEE Trans Electron Devices 15:569–57410.1109/TED.2004.823803 ↗
17. Goel A, Rewari S, Verma S, Gupta RS (2019b) Shallow extension engineered dual material surrounding gate (SEE-DM-SG) MOSFET for improved gate leakages, analysis of circuit and noise performance. AEU-Int J Electron Commun 111:15292410.1016/j.aeue.2019.152924 ↗
18. Long W, Ou H, Kuo J-M, Chin KK (1999) Dual material gate (DMG) field effect transistor. IEEE Trans Electron Devices 46:865–87010.1109/16.760391 ↗
19. Young KK (1989) Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans Electron Devices 36:399–40210.1109/16.19942 ↗
20. Zhou X (2000) Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering. IEEE Trans Electron Devices 47:113–12010.1109/16.817576 ↗
21. Zhou X, Long W (1998) A novel hetero-material gate (HMG) MOSFET for deep-submicrometer ULSI technology. IEEE Trans Electron Devices 45:2546–254810.1109/16.735743 ↗