Performance analysis of sub 10 nm regime source halo symmetric and asymmetric nanowire MOSFET with underlap engineering
Source abstract
Abstract
In this paper, we are proposing a gate oxide stack source halo symmetric and asymmetric underlap extension nanowire MOSFET with HfO2 spacer at 10 nm regime. The increased doping concentration at the source channel vicinity decreases the depletion width which increases the energy barrier levels at the source-channel interface and the lightly doped underlap increases the tunneling width in the lateral direction. Because of increased barrier width and height, the proposed device exhibits lowest OFF-state current 6.61 × 10–14 Amp and high (frac{{I}ON}{{I}OFF}) ratio 2.48 × 108. Further, the proposed device performance is analyzed for the symmetrical and asymmetrical underlap, extension length variations. The device produces the highest improvement in the performance metrics for symmetric source-drain underlap extension as compared to other variations. The (frac{{I}ON}{{I}OFF}) ratio of the device improves by 96% with symmetric source-drain underlap at LSUnlap = LDUnlap = LSDUnlap = 1.5 × LG and 76% with symmetric source-drain extension at LSExt = LDExt = LSDExt = 0.5 × LG. Furthermore, the (frac{{I}ON}{{I}OFF}) ratio of the device improves by 25% with the gate oxide stack. As a result of the lower leakage current and high (frac{{I}ON}{{I}OFF}) ratio (~ 108) even in the 10 nm regime, the proposed device is used in ultra-low power and memory applications.
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Research context
OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Ferroelectric and Negative Capacitance Devices
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (33)
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