Analysis of Temperature Dependent Effects on DC, Analog/RF and Linearity Parameters for a Delta Doped Heterojunction Vertical tunnel FET
Source abstract
Abstract
In this article, using a 3D Technology computer aided design (TCAD) simulator, a systematic investigation on the effects of temperature variations in the range of 200–400 K on various parameters of a delta doped heterojunction vertical tunnel FET (DDHvTFET) is carried out. We illustrated the DC output characteristics such as drain current, subthreshold swing (SS), threshold voltage as well as current ratio. The results indicate that while current conduction is governed by band-to-band tunneling, the vertical tunnel FET has very minimal temperature dependency, while temperature reliance rises in the OFF-state regime. The leakage current deteriorates from an order of 10−16 A to 10−12 A at elevated temperature. The percentage change for temperature variation of the device for different electrical parameters is compared with other existing TFETs. An extensive discussion on the influence of temperature variations on various Analog/RF figures of merit on the DDHvTFET indicate that the parameters directly related to the transconductance show an enhancement with decline in temperature. However, the linearity parameters of the DDHvTFET reveal that higher temperature value exhibit less distorted output. Finally, the drain current and gate voltage power spectral noise densities decrease for higher temperature values and gets saturated at higher gate voltages.
Source: openaire · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices · Integrated Circuits and Semiconductor Failure Analysis
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (48)
Show source-provided references
1. Roy K, Mukhopadhyay S, Meimand HM (2003) Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc IEEE 91:305–32710.1109/JPROC.2002.808156 ↗
2. Seabaugh AC, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98:2095–211010.1109/JPROC.2010.2070470 ↗
3. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479:329–33710.1038/nature10679 ↗
4. Ionescu AM, Michielis LD, Dagtekin N, Salvatore G, Cao J, Rusu A, Bartsch S (2011) Ultra low power: Emerging devices and their benefits for integrated circuits. IEDM Tech Dig :1611–161410.1109/IEDM.2011.6131563 ↗
5. Boucart K, Ionescu AM (2007) Double gate tunnel FET with High-k gate dielectric. IEEE Trans Electron Devices 54:1725–173310.1109/TED.2007.899389 ↗
6. Lu H, Seabaugh A (2014) Tunnel field-effect transistors: State-of-the-art. IEEE J Electron Devices Soc 2:44–4910.1109/JEDS.2014.2326622 ↗
7. Bhuwalka K, Schulze J, Eisele I (2005) Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering. IEEE Trans Electron Devices 52:909–91710.1109/TED.2005.846318 ↗
8. Kim SM, Kam H, Hu C, Liu TJK (2009) Germanium-source tunnel field effect transistors with record high ION/IOFF. Proc VLSI Symp Tech Dig :178–179
9. Toh EH et al (2008) Device design and scalability of a double-gate tunneling field-effect transistor with silicon–germanium source. Jpn J Appl Phys 47:2593–259710.1143/JJAP.47.2593 ↗
10. Schlosser M, Bhuwalka KK, Sauter M, Zilbauer T, Sulima T, Eisele I (2009) Fringing-induced drain current improvement in the tunnel field-effect transistor with high-κ gate dielectrics. IEEE Trans Electron Devices 56:100–10810.1109/TED.2008.2008375 ↗
11. Kumar S et al (2017) 2-D analytical modeling of the electrical characteristics of dual-material double-gate TFETs with a SiO2/HfO2 stacked gate-oxide structure. IEEE Trans Electron Devices 64:960–968. https://doi.org/10.1109/TED.2017.265663010.1109/TED.2017.2656630 ↗
12. Choi WY, Lee W (2010) Hetero-gate-dielectric tunneling field effect transistors. IEEE Trans Electron Devices 57:2317–231910.1109/TED.2010.2052167 ↗
13. Chen Z et al (2009) Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires. IEEE Electron Device Lett 30:754–756. https://doi.org/10.1109/LED.2009.202107910.1109/LED.2009.2021079 ↗
14. Gandhi R, Chen Z, Singh N, Banerjee K, Lee S (2011) Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (<=50 mV/decade) at room temperature. IEEE Electron Device Lett 32:437–439. https://doi.org/10.1109/LED.2011.210675710.1109/LED.2011.2106757 ↗
15. Lattanzio L, Michielis LD, Ionescu AM (2012) Complementary germanium electron–hole bilayer tunnel FET for sub-0.5-V operation. IEEE Electron Device Lett 33:167–16910.1109/LED.2011.2175898 ↗
16. Mallik A, Chattopadhyay A, Omura Y (2014) Gate-on-germanium source tunnel field-effect transistor enabling sub-0.5-V operation. Jpn J Appl Phys 53:104201-1-104201-710.7567/JJAP.53.104201 ↗
17. Chattopadhyay A, Mallik A, Omura Y (2015) Device optimization and scaling properties of a gate-on-germanium source tunnel fieldeffect transistor. Superlattice Microstruct 82:415–42910.1016/j.spmi.2015.02.022 ↗
18. Vanlalawpuia K, Bhowmick B (2019) Investigation of a Ge-source vertical TFET with delta-doped layer. IEEE Trans Electron Devices 66:4439–444510.1109/TED.2019.2933313 ↗
19. Mallik A, Chattopadhyay A (2012) Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications. IEEE Trans Electron Devices 59:888–89410.1109/TED.2011.2181178 ↗
20. Akram MW, Ghosh B (2014) Analog performance of double gate junctionless tunnel field effect transistor. J Semicond 35:07400110.1088/1674-4926/35/7/074001 ↗
21. Agopian PGD et al (2015) Influence of the source composition on the analog performance parameters of vertical nanowire TFETs. IEEE Trans Electron Devices 62:16–2210.1109/TED.2014.2367659 ↗
22. Settino F et al (2017) Understanding the potential and limitations of tunnel FETs for low-voltage analog/mixed-signal circuits. IEEE Trans Electron Devices 64:2736–274310.1109/TED.2017.2689746 ↗
23. Mallik A, Chattopadhyay A (2011) Drain-dependence of tunnel field-effect transistor characteristics: The role of the channel. IEEE Trans Electron Devices 58:4250–425710.1109/TED.2011.2169416 ↗
24. Mallik A, Chattopadhyay A, Guin S, Karmakar A (2013) Impact of a spacer-drain overlap on the characteristics of a silicon tunnel field-effect transistor based on vertical tunneling. IEEE Trans Electron Devices 60:935–94310.1109/TED.2013.2237776 ↗
25. Nirschl T, Wang PF, Hansch W, Landsiedel DS (2004) The tunneling field effect transistors (TFET): The temperature dependence, the simulation model, and its application. Proc Int Symp Circuits Syst, 713–716
26. Born M, Bhuwalka KK, Schindler M, Abilene U, Schmidt M, Sulima T, Eisele I (2006) Tunnel FET: A CMOS device for high temperature applications. Proc 25th Int Conf Microelectron, 124–12710.1109/ICMEL.2006.1650911 ↗
27. Chengy Y, Imaiz K, Jengx MC, Liuk Z, Cheny K, Hu C (1997) Modelling temperature effects of quarter micrometre MOSFETs in BSIM3v3 for circuit simulation. Semicond Sci Technol 12:1349–135410.1088/0268-1242/12/11/004 ↗
28. Agopian PGD, Martino MGV, Filho SGS, Martino JA, Rooyackers R, Leonelli D, Claeys C (2012) Temperature impact on the tunnel FET off-state current components. Solid-State Electron 78:141–14610.1016/j.sse.2012.05.053 ↗
29. Migita S, Fukuda K, Morita Y, Ota H (2012) Experimental demonstration of temperature stability of Si-tunnel FET over Si-MOSFET. Proc Silicon Nanoelectron Workshop, 1–210.1109/SNW.2012.6243315 ↗
30. Mookerjea S, Mohata D, Mayer T, Narayanan V, Datta S (2010) Temperature-dependent I–V characteristics of a vertical In0.53Ga0.47As tunnel FET. IEEE Electron Device Lett 31:564–56610.1109/LED.2010.2045631 ↗
31. Datta E, Chattopadhyay A, Mallik A, Omura Y (2020) Temperature dependence of analog performance, linearity, and harmonic distortion for a Ge-source tunnel FET. IEEE Trans Electron Devices 67:810–81510.1109/TED.2020.2968633 ↗
32. Mcdonald JA (1996) Proving they can take the heat. III-Vs Rev 9:63–6710.1016/S0961-1290(96)80200-6 ↗
33. Osman A, Osman M (2002) Investigation of high temperature effects on MOSFET transconductance (gm). Proc 4th Int High Temp Electron Conf (HITEC), 301–304
34. Ziliotto APB, Bellodi M (2008) Study of high temperature influence on MOS capacitor high frequency C-V curves behavior. IV Seminatec, São Paulo
35. Ziliotto APB, Bellodi M (2011) Evaluation of the high temperatures influence on high frequency C-V curves of MOS capacitor. ECS Trans 41:163–17310.1149/1.3629964 ↗
36. Vandenberghe WG, Sorée B, Magnus W, Groeseneken G, Fischetti MV (2011) Impact of field-induced quantum confinement in tunneling field-effect devices. Appl Phys Lett 98:14350310.1063/1.3573812 ↗
37. Beneventi GB, Gnani E, Gnudi A, Reggiani S, Baccarani G (2015) Optimization of a pocketed dual-metal-gate TFET by means of TCAD simulations accounting for quantization-induced bandgap widening. IEEE Trans Electron Devices 62:44–5110.1109/TED.2014.2371071 ↗
38. Satubbi F, Nanver LS, Scholtes TL (2006) CVD delta-doped boron surface layers for ultra-shallow junction formation. ECS Trans 3:1–1010.1149/1.2392928 ↗
39. Scappucci G (2014) Phosphorus delta-doping in germanium. 7th Int. Silicon-Germanium Technol. Device Meeting (ISTDM), 27–2810.1109/ISTDM.2014.6874623 ↗
40. Sentaurus Device User Guide (2017) Synopsys, Inc., Mountain View, CA
41. Kao KH, Verhulst AS, Vandenberghe WG, Sorée B, Groeseneken G, Meyer KD (2012) Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans Electron Devices 59:292–30110.1109/TED.2011.2175228 ↗
42. Vanlalawmpuia K, Bhowmick B (2021) Study on induced work-function variation of titanium metal gate on various electrical parameters for delta-doped layer germanium source vertical tunnel FET. J Comput Electron. https://doi.org/10.1007/s10825-021-01686-810.1007/s10825-021-01686-8 ↗
43. Narang R, Saxena M, Gupta RS, Gupta M (2013) Impact of temperature variations on the device and circuit performance of tunnel FET: A Simulation Study. IEEE Trans Nanotechnol 12:951–95710.1109/TNANO.2013.2276401 ↗
44. Nigam K, Pandey S, Kondekar PN, Sharma D (2016) Temperature sensitivity analysis of polarity controlled electrically doped hetero-TFET. 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Lisbon, Portugal10.1109/PRIME.2016.7519465 ↗
45. Madan J, Chaujar R (2018) Temperature associated reliability issues of heterogeneous gate dielectric—Gate all around—Tunnel FET. IEEE Trans Nanotechnol 17:41–4810.1109/TNANO.2017.2650209 ↗
46. Goswami R, Bhowmick B, Baishya S (2016) Effect of scaling on noise in circular gate TFET and its application as a digital inverter. Microelectron J 53:16–2410.1016/j.mejo.2016.04.009 ↗
47. Das D, Chakraborty U (2021) Effect of dielectric pocket for controlling ambipolar conduction in TFET and analysis of noise and temperature sensitivity. Indian J Phys. https://doi.org/10.1007/s12648-021-02054-910.1007/s12648-021-02054-9 ↗
48. Pandey R, Rajamohanan B, Liu H, Narayanan V, Datta S (2014) Electrical noise in Heterojunction Interband tunnel FETs. IEEE Trans Electron Devices 61:552–56010.1109/TED.2013.2293497 ↗