Low–power and High-speed Multi-operational Shift Register on Silicon Using Bi-enabled Pulsed Latch

This paper presents a low-power and high-speed multi-operational shift register on silicon designed using proposed bi-enabled pulsed latch. Multi operation in shift register is achieved through bi-enabled pulsed latches and low power consumption is achieved by replacing flip-flops with pulsed latches. Achieving multiple operations from shift register and Linear Feedback Shift Register (LFSR) operation in a single hardware is the exclusive feature of the proposed architecture. The proposed architecture uses a bi-enabled pulsed latchesand multiplexers to enhance the different mode selection capabilities. A 256-bit Multi-operational shift register using bi-enabled pulsed latches is designed in 180nm CMOS process with VDD = 1.8 V. The frontend design of proposed 256 bit Multi-operational shift register saves 33 % area and 66 %power consumption, than the conventional shift register design made by flip-flop with sub shift register length of 4(K=4). The frontend design of proposed 256 bit shift register saves 47.3 % power consumption than the existing pulsed latch shift register with sub shift register length of 4. The proposed bi-enabled pulsed latch-based shift register can execute five different operations with different mode selection capabilities whereas in existing pulsed latch based shift register shows the single possible operation alone. The backend design shows that the proposed multi-operational shift register achieves the chip power reduction, less computation time, more positive setup slack and power delay product when compared to existing pulsed latch based shift register due to the introduction of bi-enabled pulsed latch with less switching activity.