A write buffer design based on stable and area-saving embedded SRAM for flash applications
Source abstract
Abstract
This paper presents an embedded SRAM design for page buffer applications in flash memories. The page buffer was implemented with a newly proposed self-adaptive timing control circuit, an area-saving sense-latch circuit and 6T SRAM cell unit. A 2Kb SRAM macro with area of 135µm × 180µm has been implemented and applied in a 128Mb NOR flash memory with SMIC 65nm flash memory technology. Both simulation and chip test results show that SRAM page buffer is benefitial for high density flash memory design.
Source: openaire · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Advanced Data Storage Technologies · Parallel Computing and Optimization Techniques · Semiconductor materials and devices
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References (5)
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