In-situ measurement of solder joint strength in board-mounted chip-scale packages using a quantitative laser spallation technique

A previously developed laser spallation (LS) technique for measuring the interface strengths of planar films is modified to determine the interfacial tensile strengths of solder joints, in situ, in board-mounted chip-scale packages (CSPs). The new technique is demonstrated on packages with bare Cu pads and Pb-free solders. The solder/pad interface strength is determined by first using a laser-generated stress wave to separate the geometrically heterogeneous interface, in situ, and then quantifying the failure stress by a combination of interferometry and wave mechanics simulation. The solder to pad interfacial strengths were found to be 705 ± 102, 510 ± 71, and 369 ± 55 MPa for packages stressed by baking at 150 °C for 0, 48, and 100 h, respectively. The interface strengths were found to be roughly proportional to the critical laser energies for separation of solder joints. Thus, it may suffice to use the critical laser energy as a parameter for the purposes of material selection and solder joint quality inspection during manufacturing. The quantitative capability of the LS test for testing board-level packages now provides an opportunity to enhance the board-level drop test that is widely conducted in the industry today.