Viscoelastic Simulation of Stress and Warpage for Memory Chip 3D-Stacked Package
Source abstract
Abstract
Three-dimensional-stacked packaging technology is widely used in memory chip packaging, which can greatly increase the utilization ratio of the packaging area. However, problems with the reliability of 3D-stacked packaging are also becoming more and more serious. In this paper, first, a dynamic mechanical analyzer is used to obtain the EMC viscoelasticity parameters. Then, the influence trend of different factors, such as EMC, die bond material and chip, on the performance of the memory chip 3D-stacked packaging under a fixed temperature cyclic loading condition is explored by the FE method.
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Research context
OpenAlex topics: Electronic Packaging and Soldering Technologies · 3D IC and TSV technologies · Material Properties and Processing
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
College of Mechanical and Electrical Engineering, Guilin University of Electronic Science Technology, Guilin 541004, China
Funding
Innovation-Driven Development Project of Guangxi Province · Key R & D Plan Project of Guangxi Province · National Natural Science Foundation of China · Guilin Science Research and Technology Development Program
References (24)
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