FPGA Accelerators for Computing Interatomic Potential-Based Molecular Dynamics Simulation for Gold Nanoparticles: Exploring Different Communication Protocols
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Abstract
Molecular Dynamics (MD) simulation for computing Interatomic Potential (IAP) is a very important High-Performance Computing (HPC) application. MD simulation on particles of experimental relevance takes huge computation time, ... | Find, read and cite all the research you need on Tech Science Press
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Research context
OpenAlex topics: Molecular Communication and Nanonetworks · Quantum Computing Algorithms and Architecture · Quantum-Dot Cellular Automata
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References (27)
Show source-provided references
1. Accelerating high performance computing applications: Using CPUs, GPUs, Hybrid CPU/GPU, and FPGAs
2. A hybrid GPU-FPGA based design methodology for enhancing machine learning applications performance10.1007/s12652-019-01357-4 ↗
3. Trends of CPU, GPU and FPGA for high-performance computing
4. Simple communication with FPGA device over ethernet interface
5. Heterogeneous computing platform based on CPU+FPGA and working modes
6. vCUDA: GPU-accelerated high-performance computing in virtual machines10.1109/TC.2011.112 ↗
7. Resource scheduling strategy for performance optimization based on heterogeneous CPU-GPU platform
8. Achieving high performance with FPGA-based computing10.1109/MC.2007.79 ↗
9. Spherical harmonics based descriptor for neural network potentials: Structure and dynamics of Au147 nanocluster10.1063/1.4983392 ↗
10. Generalized Verlet algorithm for efficient molecular dynamics simulations with long-range interactions
11. Velocity Verlet algorithm for dissipative-particle-dynamics-based models of suspensions10.1103/PhysRevE.59.3733 ↗
12. Heterogeneous parallelization and acceleration of molecular dynamics simulations in GROMACS
13. Accelerators for classical molecular dynamics simulations of biomolecules10.1021/acs.jctc.1c01214 ↗
14. GPU-accelerated molecular dynamics: State-of-art software performance and porting from Nvidia CUDA to AMD HIP10.1177/10943420211008288 ↗
15. Fully integrated FPGA molecular dynamics simulations
16. FPGA optimized accelerator of DCNN with fast data readout and multiplier sharing strategy
17. Hardware/software approach to molecular dynamics on reconfigurable computers
18. Execution of complete molecular dynamics simulations on multiple FPGAs
19. FPGA accelerator for machine learning interatomic potential-based molecular dynamics of gold nanoparticles10.1109/ACCESS.2022.3165650 ↗
20. Inc Xilinx, “KC705 evaluation board for the Kintex-7 FPGA user guide,” version: UG810 v1.9, USA, Feb. 4, 2019. Accessed: Mar. 13, 2023. [Online]. Available: https://docs.amd.com/v/u/en-US/ug810_KC705_Eval_Bd
21. Soft-core processors for embedded systems
22. Inc Xilinx, “MicroBlaze processor reference guide,” version: UG984 v2021.2, USA, Oct. 27, 2021. Accessed: Nov. 15, 2022. [Online]. Available: https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf
23. Inc Xilinx, “AXI UART Lite LogiCORE IP product guide,” version: PG142 v2017. 2, USA, Apr. 5, 2017. Accessed: Dec. 6, 2022. [Online]. Available: https://docs.amd.com/v/u/en-US/pg142-axi-uartlite
24. Inc Xilinx, “AXI Ethernet lite MAC LogiCORE IP product guide,” version: PG135 v2021. 3, USA, Nov. 2, 2021. Accessed: Feb. 2, 2023. [Online]. Available: https://docs.amd.com/r/en-US/pg135-axi-ethernetlite/AXI-Ethernet-Lite-MAC-v3.0-LogiCORE-IP-Product-Guide
25. FPGA Computing10.1109/MM.2021.3088975 ↗
26. Inc Xilinx, “Vivado design suite user guide: Embedded processor hardware design,” version: UG898 v2021.1, USA, Jun. 16, 2021. Accessed: Jan. 17, 2023. [Online]. Available: https://docs.amd.com/v/u/2021.1-English/ug898-vivado-embedded-design
27. Inc Xilinx, “UltraFast embedded design methodology guide,” version: UG1046 v2018.2.3, USA, Apr. 20, 2018. Accessed: Aug. 6, 2023. [Online]. Available: https://docs.amd.com/v/u/en-US/ug1046-ultrafast-design-methodology-guide