A Process for Multi‐level Copper‐polyimide High Density Interconnect Structures, Flex Circuits and TAB Tape

This paper describes a process for fabricating high density multilayer polyimide‐metal interconnect structures for packaging applications such as multichip carriers, flex circuits and multiconductor TAB tape. The process combines the advantages of a semi‐additive via process, such as the uniformity of the electroplated vias and the ability to produce vertical stacked‐up vias, with a processing sequence that does not require a temporary plating mask for vias or a planarisation/via‐top‐exposure step. The key idea behind the process is the fact that all of the circuitry in a multilayer interconnect is electrically connected to the upper conductor layer. This allows building the interconnect upside down on a temporary substrate using a continuous bottom level metallisation as an electrode for plating all level vias. This layer eventually becomes the upper conductor. After the processing is complete, the multilayer interconnect structure is either released from the temporary substrate, resulting in a multilevel multichip interconnect. After the multilevel structure is released, the continuous metal, which was on the bottom, is patterned with the upper conductor pattern, isolating the individual circuits. As an example, a process sequence for building a three‐metal‐layer substrate with 5 ?m by 30 ?m copper conductors, 50 ?m by 50 ?m square vias with 15 ?m interlayer polyimide is presented along with electrical test data. The process can be extended to producing mixed‐geometry multiconductor tape structures for TAB that result in tape frames with controlled conductor properties, and offer the potential for finer geometries for TAB fingers than are now available through conventional TAB tape processes.