Effects of conductor surface condition on signal integrity

The evolution of digital electronic systems to ever‐faster pulse rise times has placed increased demands on printed wiring board (PWB) materials. Signal loss associated with dielectric materials has driven development and commercialization of cost‐effective low loss laminate materials. In order to provide a better understanding of conductor material and surface finish choices, efforts have been made to quantify the impacts of these factors on loss. An alternative test approach has been identified which provides a measure of conductor performance, decoupled from both system geometry and the influence of laminate material.