Optimal printed wiring board design for high I/O density chip size packages

This paper addresses the issues involved in the design of high‐density boards for high‐density chip scale packages. An analytical model is developed to calculate the number of I/Os accommodated by the printed wiring board. The model is placed under constraints of package area, package I/O pitch, number of lanes per channel, PWB device feature sizes (I/O, via pad, signal traces), number of routing layers on board and the partition of routing regions on each level. The model is utilized to study the precise impact of number of routing layers and device feature size on the I/O density of PCB. The scheme for optimally partitioning each layer to achieve maximum I/O density is discussed. Specific guidelines are provided pertaining to the usage of higher board layers and/or reduced device feature sizes to design high‐density boards for future electronic products.