Reliability testing for microvias in printed wire boards

Purpose The purpose of this paper is to identify and expand upon the understanding of the reliability of high density interconnect (HDI) technologies containing multi‐level microvia interconnections with 2, 3 or 4 stacked and staggered configured structures. Design/methodology/approach Microvia testing was performed with interconnect stress testing (IST) using a modified methodology documented in the IPC test methods manual TM650, Method 2.6.26, titled DC current induced thermal cycle test. The IST coupon designs utilize mathematical modeling, in combination with prior experience in the fields of printed wiring board (PWB) processing, chemistry, materials and statistics, to improve the sensitivity of testing. Findings Single and 2 stack microvias are generally the most robust type of copper interconnection used in HDI applications, 3 stack and 4 stack require greater discipline to assure product reliability. Ranking the inherent reliability of 3 stack and 4 stack structures to other interconnects like plated through holes, blind, or buried vias, may need to be reconsidered in future reliability test programs. Research limitations/implications This work was focused on the reliability of bare board and does not address failure modes associated with the additional stresses applied to the microvia structures created by the devices and their associated solder joints formed during surface mount assembly and rework operations. Originality/value This paper was written to improve the understanding of various aspects of design and their influence on reliability for stacked and staggered microvia structures. The design function must understand the physical construction as a critical influence on microvia reliability that should be taken into consideration in parallel with the electrical requirements.